{"title":"AREAL:模拟布局的自动推理专家","authors":"H. Ahmad, R. Mack","doi":"10.1109/EDTC.1994.326803","DOIUrl":null,"url":null,"abstract":"A system for analogue circuit layout generation is presented which utilises knowledge and geometric reasoning to prune the design space. Topological and geometric constraints, deduced from analogue and connectivity information, are expressed in the form of Boolean relations, and are imposed and preserved throughout the solution by means of a Boolean-constraint-solver. The reduced design space is then explored by a controlled branch-and-bound process to find an optimal solution.<<ETX>>","PeriodicalId":244297,"journal":{"name":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","volume":"52 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1994-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"AREAL: automated reasoning expert for analogue layout\",\"authors\":\"H. Ahmad, R. Mack\",\"doi\":\"10.1109/EDTC.1994.326803\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A system for analogue circuit layout generation is presented which utilises knowledge and geometric reasoning to prune the design space. Topological and geometric constraints, deduced from analogue and connectivity information, are expressed in the form of Boolean relations, and are imposed and preserved throughout the solution by means of a Boolean-constraint-solver. The reduced design space is then explored by a controlled branch-and-bound process to find an optimal solution.<<ETX>>\",\"PeriodicalId\":244297,\"journal\":{\"name\":\"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC\",\"volume\":\"52 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1994-02-28\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EDTC.1994.326803\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EDTC.1994.326803","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
AREAL: automated reasoning expert for analogue layout
A system for analogue circuit layout generation is presented which utilises knowledge and geometric reasoning to prune the design space. Topological and geometric constraints, deduced from analogue and connectivity information, are expressed in the form of Boolean relations, and are imposed and preserved throughout the solution by means of a Boolean-constraint-solver. The reduced design space is then explored by a controlled branch-and-bound process to find an optimal solution.<>
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