一种新的减小时钟摆动触发器:nand型保持触发器(NDKFF)

Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285) Pub Date : 2002-08-07 DOI:10.1109/CICC.2002.1012782

M. Tokumasu, H. Fujii, M. Ohta, T. Fuse, A. Kameyama

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引用次数: 10

摘要

提出了一种新的减小时钟摆动触发器，称为nand型保持触发器(NDKFF)。与HSFF和RCSFF等传统的减小时钟摆动触发器相比，NDKFF的配置简单，不需要额外的时钟驱动器，也不需要额外的nand/ p井。与混合锁存器触发器相比，在0.25 /spl mu/m CMOS技术下，触发器功耗节省52%，时钟功耗节省64%。此外，CLK-to-Q延迟与传统的c2mos型主从触发器相当。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A new reduced clock-swing flip-flop: NAND-type keeper flip-flop (NDKFF)

A new reduced clock-swing flip-flop, named NAND-type Keeper Flip-Flop (NDKFF) is proposed. Compared with other conventional reduced clock-swing flip-flops such as HSFF and RCSFF, NDKFF features a simple configuration, which does not have additional clock drivers or does not have additional nand/or p-wells. Compared with the hybrid-latch flip-flop, 52% of the flip-flop power and 64% of the clocking power are saved in the case of 0.25 /spl mu/m CMOS technology. Moreover CLK-to-Q delay is comparable to that of conventional C2MOS-type master-slave flip-flop.

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Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)

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