使用 GitLab CI 实现 FPGA 设计构建流程自动化

IF 1.7 4区 计算机科学 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE IEEE Embedded Systems Letters Pub Date : 2023-09-12 DOI:10.1109/LES.2023.3314148
Chimezie Eguzo;Benedikt Scherer;Daniel Keßel;Ilja Bekman;Matthias Streun;Mario Schlosser;Stefan van Waasen
{"title":"使用 GitLab CI 实现 FPGA 设计构建流程自动化","authors":"Chimezie Eguzo;Benedikt Scherer;Daniel Keßel;Ilja Bekman;Matthias Streun;Mario Schlosser;Stefan van Waasen","doi":"10.1109/LES.2023.3314148","DOIUrl":null,"url":null,"abstract":"Building and testing software for embedded systems can be challenging with an impact on delivery time, design reproducibility, and collaboration among project contributors. To accelerate project development, presented here is an automated build flow that utilizes Xilinx PetaLinux, and field programmable gate array (FPGA) hardware description and integrates with the GitLab continuous integration and continuous deployment (CI/CD) framework for embedded targets. This build flow automates the complete process of FPGA implementation, PetaLinux configuration, and cross-compilation of software essentials for the target system-on-chip (SoC). The system has been successfully deployed in cross-compiling the control and command toolset for the Positron Emission Tomography scanner (PhenoPET) and the implementation of the message queuing telemetry transport (MQTT) service on a Xilinx Zynq Ultrascale MPSoC. This approach can be easily adapted to other projects with specific requirements.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"16 2","pages":"227-230"},"PeriodicalIF":1.7000,"publicationDate":"2023-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"On Automating FPGA Design Build Flow Using GitLab CI\",\"authors\":\"Chimezie Eguzo;Benedikt Scherer;Daniel Keßel;Ilja Bekman;Matthias Streun;Mario Schlosser;Stefan van Waasen\",\"doi\":\"10.1109/LES.2023.3314148\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Building and testing software for embedded systems can be challenging with an impact on delivery time, design reproducibility, and collaboration among project contributors. To accelerate project development, presented here is an automated build flow that utilizes Xilinx PetaLinux, and field programmable gate array (FPGA) hardware description and integrates with the GitLab continuous integration and continuous deployment (CI/CD) framework for embedded targets. This build flow automates the complete process of FPGA implementation, PetaLinux configuration, and cross-compilation of software essentials for the target system-on-chip (SoC). The system has been successfully deployed in cross-compiling the control and command toolset for the Positron Emission Tomography scanner (PhenoPET) and the implementation of the message queuing telemetry transport (MQTT) service on a Xilinx Zynq Ultrascale MPSoC. This approach can be easily adapted to other projects with specific requirements.\",\"PeriodicalId\":56143,\"journal\":{\"name\":\"IEEE Embedded Systems Letters\",\"volume\":\"16 2\",\"pages\":\"227-230\"},\"PeriodicalIF\":1.7000,\"publicationDate\":\"2023-09-12\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Embedded Systems Letters\",\"FirstCategoryId\":\"94\",\"ListUrlMain\":\"https://ieeexplore.ieee.org/document/10247255/\",\"RegionNum\":4,\"RegionCategory\":\"计算机科学\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q3\",\"JCRName\":\"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Embedded Systems Letters","FirstCategoryId":"94","ListUrlMain":"https://ieeexplore.ieee.org/document/10247255/","RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
引用次数: 0

摘要

嵌入式系统软件的构建和测试具有挑战性,会对交付时间、设计可重复性和项目贡献者之间的协作产生影响。为了加快项目开发,本文介绍了一种自动构建流程,它利用赛灵思 PetaLinux 和现场可编程门阵列(FPGA)硬件描述,并与针对嵌入式目标的 GitLab 持续集成和持续部署(CI/CD)框架集成。该构建流程可自动完成 FPGA 实施、PetaLinux 配置和目标片上系统(SoC)软件要件交叉编译的整个过程。该系统已成功应用于正电子发射断层扫描仪(PhenoPET)控制和命令工具集的交叉编译,以及 Xilinx Zynq Ultrascale MPSoC 上消息队列遥测传输(MQTT)服务的实施。这种方法可轻松适用于具有特定要求的其他项目。
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On Automating FPGA Design Build Flow Using GitLab CI
Building and testing software for embedded systems can be challenging with an impact on delivery time, design reproducibility, and collaboration among project contributors. To accelerate project development, presented here is an automated build flow that utilizes Xilinx PetaLinux, and field programmable gate array (FPGA) hardware description and integrates with the GitLab continuous integration and continuous deployment (CI/CD) framework for embedded targets. This build flow automates the complete process of FPGA implementation, PetaLinux configuration, and cross-compilation of software essentials for the target system-on-chip (SoC). The system has been successfully deployed in cross-compiling the control and command toolset for the Positron Emission Tomography scanner (PhenoPET) and the implementation of the message queuing telemetry transport (MQTT) service on a Xilinx Zynq Ultrascale MPSoC. This approach can be easily adapted to other projects with specific requirements.
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来源期刊
IEEE Embedded Systems Letters
IEEE Embedded Systems Letters Engineering-Control and Systems Engineering
CiteScore
3.30
自引率
0.00%
发文量
65
期刊介绍: The IEEE Embedded Systems Letters (ESL), provides a forum for rapid dissemination of latest technical advances in embedded systems and related areas in embedded software. The emphasis is on models, methods, and tools that ensure secure, correct, efficient and robust design of embedded systems and their applications.
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