通过修剪长链提高量子退火器的覆盖范围和可靠性

IF 1.4 3区 计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE IEEE Computer Architecture Letters Pub Date : 2023-12-06 DOI:10.1109/LCA.2023.3340030
Ramin Ayanzadeh;Moinuddin Qureshi
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引用次数: 0

摘要

模拟量子计算机(QC),如 D-Wave 的量子退火器(QAs)和 QuEra 的中性原子平台,在计算能力上可与数字量子计算机相媲美。现有的 QA 拥有超过 5,700 个量子比特,但它们的单指令操作模型无法使用 SWAP 操作使物理距离较远的量子比特相邻。取而代之的是,QA 使用嵌入过程将多个物理量子比特链在一起,代表了具有更高连通性的程序量子比特,并将 QA 的有效容量最多降低了 33 倍。我们观察到,嵌入后,近 25% 的物理量子比特仍未使用,被困在链之间。此外,我们还观察到了链长度的 "幂律 "分布,其中少数占主导地位的链拥有更多的量子比特,从而对量子比特利用率和隔离度产生了更为显著的影响。利用这些洞察力,我们提出了 Skipper,这是一种软件技术,旨在通过跳过优势链并用两个测量结果替代其程序量子比特来增强 QA 的容量和保真度。通过使用 5761 个量子比特的 QA,我们观察到通过跳过多达 11 个链,容量增加了多达 59%(平均 28%),误差减少了多达 44%(平均 33%)。
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Enhancing the Reach and Reliability of Quantum Annealers by Pruning Longer Chains
Analog Quantum Computers (QCs), such as D-Wave's Quantum Annealers ( QAs ) and QuEra's neutral atom platform, rival their digital counterparts in computing power. Existing QAs boast over 5,700 qubits, but their single-instruction operation model prevents using SWAP operations for making physically distant qubits adjacent. Instead, QAs use an embedding process to chain multiple physical qubits together, representing a program qubit with higher connectivity and reducing effective QA capacity by up to 33x. We observe that, post-embedding, nearly 25% of physical qubits remain unused, becoming trapped between chains. Additionally, we observe a “Power-Law” distribution in the chain lengths, where a few dominant chains possess significantly more qubits, thereby exerting a considerably more significant impact on both qubit utilization and isolation. Leveraging these insights, we propose Skipper , a software technique designed to enhance the capacity and fidelity of QAs by skipping dominant chains and substituting their program qubit with two measurement outcomes. Using a 5761-qubit QA, we observed that by skipping up to eleven chains, the capacity increased by up to 59% (avg 28%), and the error decreased by up to 44% (avg 33%).
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来源期刊
IEEE Computer Architecture Letters
IEEE Computer Architecture Letters COMPUTER SCIENCE, HARDWARE & ARCHITECTURE-
CiteScore
4.60
自引率
4.30%
发文量
29
期刊介绍: IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. Submissions are welcomed on any topic in computer architecture, especially but not limited to: microprocessor and multiprocessor systems, microarchitecture and ILP processors, workload characterization, performance evaluation and simulation techniques, compiler-hardware and operating system-hardware interactions, interconnect architectures, memory and cache systems, power and thermal issues at the architecture level, I/O architectures and techniques, independent validation of previously published results, analysis of unsuccessful techniques, domain-specific processor architectures (e.g., embedded, graphics, network, etc.), real-time and high-availability architectures, reconfigurable systems.
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