在基于插值的模型检验中利用部分变量赋值

IF 0.7 4区计算机科学 Q3 COMPUTER SCIENCE, THEORY & METHODS Formal Methods in System Design Pub Date : 2019-11-07 DOI:10.1007/s10703-019-00342-z

Pavel Jancík, J. Kofroň, Leonardo S. Alt, Grigory Fedyukovich, A. Hyvärinen, N. Sharygina

引用次数: 1

查看原文

微信好友朋友圈 QQ好友复制链接

本刊更多论文

Exploiting partial variable assignment in interpolation-based model checking

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

Formal Methods in System Design 工程技术-计算机：理论方法

CiteScore

2.00

自引率

12.50%

发文量

审稿时长

>12 weeks

期刊介绍： The focus of this journal is on formal methods for designing, implementing, and validating the correctness of hardware (VLSI) and software systems. The stimulus for starting a journal with this goal came from both academia and industry. In both areas, interest in the use of formal methods has increased rapidly during the past few years. The enormous cost and time required to validate new designs has led to the realization that more powerful techniques must be developed. A number of techniques and tools are currently being devised for improving the reliability, and robustness of complex hardware and software systems. While the boundary between the (sub)components of a system that are cast in hardware, firmware, or software continues to blur, the relevant design disciplines and formal methods are maturing rapidly. Consequently, an important (and useful) collection of commonly applicable formal methods are expected to emerge that will strongly influence future design environments and design methods.

期刊最新文献

Abstraction Modulo Stability PAC statistical model checking of mean payoff in discrete- and continuous-time MDP A verified durable transactional mutex lock for persistent x86-TSO Formally understanding Rust’s ownership and borrowing system at the memory level The hexatope and octatope abstract domains for neural network verification