一个672-nW, 670-nVrms的心电采集AFE与容噪心跳检测器

IF 2.4 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC IEEE open journal of circuits and systems Pub Date : 2023-01-01 DOI:10.1109/OJCAS.2023.3237839
Yanhan Zeng;Zhixian Li;Weijian Chen;Wei Zhou;Yuchen Bao;Yongsen Chen;Yongfu Li
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引用次数: 0

摘要

提出了一种具有容噪心跳检测器的心电图采集模拟前端(AFE)。在AFE中加入了源退化和跨导自举技术,以降低放大器的1/f噪声。此外,斩波调制、直流伺服环路(DSL)和预充电技术相结合,减少了来自环境的干扰。提出了一种带对称比较环路的HB检测器混合信号实现方案,降低了功耗和面积,并通过自适应阈值抑制了运动伪影干扰。该电路采用$0.18 ~\mu \text{m}$ CMOS工艺实现,在1.2 v电源下,电路面积仅为$0.122 mm^{2}$,功耗为$0.62 ~\mu \text{W}$,其中AFE和HB探测器功耗分别为507 nW和110 nW。仿真结果表明,AFE的增益范围为30 ~ 45 dB, CMRR范围为65 ~ 105 dB。输入参考噪声为670 nVrms,中频增益为42 dB,带宽范围为0.5 Hz至1 kHz。
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A 672-nW, 670-nVrms ECG Acquisition AFE With Noise-Tolerant Heartbeat Detector
This paper presents an electrocardiogram acquisition analog front-end (AFE) with a noise tolerant heartbeat (HB) detector. Source degradation and transconductance bootstrap techniques are incorporated into the AFE to reduce the 1/f noise of the amplifier. Furthermore, the chopper modulation, DC-servo loop (DSL) and pre-charge technology are combined to reduce interference from the environment. A mixed-signal implementation of HB detector with the symmetric-comparison loop is proposed to reduce the power consumption and area, which also suppresses motion artifact interference by adaptive thresholds. Implemented in $0.18 ~\mu \text{m}$ CMOS process, the circuit only occupies an area of $0.122 mm^{2}$ and consumes $0.62 ~\mu \text{W}$ at a 1.2-V supply, of which AFE and HB detector consume 507 nW and 110 nW, respectively. Simulation results show that the gain and the CMRR of AFE range from 30–45 dB and 65–105 dB, respectively. The input-referred noise is 670 nVrms with a mid-band gain of 42 dB and a bandwidth ranging from 0.5 Hz to 1 kHz.
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