高速有线发射机的设计技术

IEEE Open Journal of the Solid-State Circuits Society Pub Date : 2021-09-14 DOI:10.1109/OJSSCS.2021.3112398

Behzad Razavi

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引用次数: 3

摘要

以每秒数十吉比特的速度运行的有线发射机带来了具有挑战性的设计问题，从有限的带宽到对抖动的严重敏感性。本文介绍了在45nm CMOS技术中允许高达80Gb/s数据速率的许多模拟和数字电路技术。PAM4原型提供630 mV$_{pp}$的输出摆幅，时钟抖动为205 fs$_{rms}$，同时绘制44 mW。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Design Techniques for High-Speed Wireline Transmitters

Wireline transmitters operating at tens of gigabits per second pose challenging design issues ranging from limited bandwidths to severe sensitivity to jitter. This paper presents a number of analog and digital circuit techniques that allow data rates as high as 80 Gb/s in 45-nm CMOS technology. A PAM4 prototype delivers an output swing of 630 mV

$_{pp}$

with a clock jitter of 205 fs

$_{rms}$

while drawing 44 mW.

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