{"title":"UART IP核的设计与仿真分析","authors":"Shihua Tong","doi":"10.1109/MACE.2011.5988319","DOIUrl":null,"url":null,"abstract":"Based on mastering SOPC and Quartus II, designed UART IP Core, and an integrity design proposal is given out. The proposal is embedded in FPGA chip. The transmitter module, receiver module and baud rate generator are simulated and analyses. The experiments results show that the design method is compact and practical, and the circuit is stable, reliable, and strong flexibility.","PeriodicalId":6400,"journal":{"name":"2011 Second International Conference on Mechanic Automation and Control Engineering","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2011-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Design and simulation analysis of UART IP Core\",\"authors\":\"Shihua Tong\",\"doi\":\"10.1109/MACE.2011.5988319\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Based on mastering SOPC and Quartus II, designed UART IP Core, and an integrity design proposal is given out. The proposal is embedded in FPGA chip. The transmitter module, receiver module and baud rate generator are simulated and analyses. The experiments results show that the design method is compact and practical, and the circuit is stable, reliable, and strong flexibility.\",\"PeriodicalId\":6400,\"journal\":{\"name\":\"2011 Second International Conference on Mechanic Automation and Control Engineering\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2011-07-15\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2011 Second International Conference on Mechanic Automation and Control Engineering\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/MACE.2011.5988319\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 Second International Conference on Mechanic Automation and Control Engineering","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MACE.2011.5988319","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Based on mastering SOPC and Quartus II, designed UART IP Core, and an integrity design proposal is given out. The proposal is embedded in FPGA chip. The transmitter module, receiver module and baud rate generator are simulated and analyses. The experiments results show that the design method is compact and practical, and the circuit is stable, reliable, and strong flexibility.
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