{"title":"基于Shannon全加法器的可控加减法单元设计","authors":"S. Choubey, Rajesh Kumar Paul","doi":"10.15662/IJAREEIE.2015.0402033","DOIUrl":null,"url":null,"abstract":"This paper deals with design of controlled adder /subtractor cell using Shannon based full adder with pass transistor logic. The proposed adder used only 14 transistors for full adder implementation. Simulations were performed by Microwind 3.1 and DSCH 2 VLSI CAD tools and BSIM 4 for parametric analysis of various features. The analysis is done on the basis of power consumption, delay and area occupied and theses are compared with previous papers and we are good to enhance these parameters.","PeriodicalId":13702,"journal":{"name":"International Journal of Advanced Research in Electrical, Electronics and Instrumentation Energy","volume":"53 1","pages":"738-742"},"PeriodicalIF":0.0000,"publicationDate":"2015-04-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Design of Controlled Adder /Subtractor CellUsing Shannon Based Full Adder\",\"authors\":\"S. Choubey, Rajesh Kumar Paul\",\"doi\":\"10.15662/IJAREEIE.2015.0402033\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper deals with design of controlled adder /subtractor cell using Shannon based full adder with pass transistor logic. The proposed adder used only 14 transistors for full adder implementation. Simulations were performed by Microwind 3.1 and DSCH 2 VLSI CAD tools and BSIM 4 for parametric analysis of various features. The analysis is done on the basis of power consumption, delay and area occupied and theses are compared with previous papers and we are good to enhance these parameters.\",\"PeriodicalId\":13702,\"journal\":{\"name\":\"International Journal of Advanced Research in Electrical, Electronics and Instrumentation Energy\",\"volume\":\"53 1\",\"pages\":\"738-742\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-04-08\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"International Journal of Advanced Research in Electrical, Electronics and Instrumentation Energy\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.15662/IJAREEIE.2015.0402033\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"International Journal of Advanced Research in Electrical, Electronics and Instrumentation Energy","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.15662/IJAREEIE.2015.0402033","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Design of Controlled Adder /Subtractor CellUsing Shannon Based Full Adder
This paper deals with design of controlled adder /subtractor cell using Shannon based full adder with pass transistor logic. The proposed adder used only 14 transistors for full adder implementation. Simulations were performed by Microwind 3.1 and DSCH 2 VLSI CAD tools and BSIM 4 for parametric analysis of various features. The analysis is done on the basis of power consumption, delay and area occupied and theses are compared with previous papers and we are good to enhance these parameters.
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