{"title":"基于OpenSPRAC架构的高速缓存交叉栏设计","authors":"Xi-chuan Wang, Bin-feng Qian","doi":"10.1109/ICEPT.2008.4606979","DOIUrl":null,"url":null,"abstract":"Multi-core processor is widely used on the server and desktop computer nowadays. This paper describes the structure of a cache crossbar which used in the multi-core processor SPARC T2. The cores can use the cache crossbar to exchange the data in the L2 cache banks. The multi cores can communicate among each other core by sharing the data in the L2 cache banks. And with the analysis of the CCX, this paper provides a protocol for connecting multi cores and cache banks. The cache crossbar is implemented in SMIC 0.13 mum with design compiler and can run at 200 MHz.","PeriodicalId":6324,"journal":{"name":"2008 International Conference on Electronic Packaging Technology & High Density Packaging","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2008-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"The design of the cache crossbar based on OpenSPRAC architecture\",\"authors\":\"Xi-chuan Wang, Bin-feng Qian\",\"doi\":\"10.1109/ICEPT.2008.4606979\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Multi-core processor is widely used on the server and desktop computer nowadays. This paper describes the structure of a cache crossbar which used in the multi-core processor SPARC T2. The cores can use the cache crossbar to exchange the data in the L2 cache banks. The multi cores can communicate among each other core by sharing the data in the L2 cache banks. And with the analysis of the CCX, this paper provides a protocol for connecting multi cores and cache banks. The cache crossbar is implemented in SMIC 0.13 mum with design compiler and can run at 200 MHz.\",\"PeriodicalId\":6324,\"journal\":{\"name\":\"2008 International Conference on Electronic Packaging Technology & High Density Packaging\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2008-07-28\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2008 International Conference on Electronic Packaging Technology & High Density Packaging\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICEPT.2008.4606979\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 International Conference on Electronic Packaging Technology & High Density Packaging","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICEPT.2008.4606979","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
The design of the cache crossbar based on OpenSPRAC architecture
Multi-core processor is widely used on the server and desktop computer nowadays. This paper describes the structure of a cache crossbar which used in the multi-core processor SPARC T2. The cores can use the cache crossbar to exchange the data in the L2 cache banks. The multi cores can communicate among each other core by sharing the data in the L2 cache banks. And with the analysis of the CCX, this paper provides a protocol for connecting multi cores and cache banks. The cache crossbar is implemented in SMIC 0.13 mum with design compiler and can run at 200 MHz.
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