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引用次数: 14

摘要

采用0.13μm CMOS 1P6M工艺实现了一种高PSR低降差(LDO)紧凑型稳压器,其峰值负载电流(IL)为100μA。通过实现一个纳米功率带隙参考电路,在1.2 v电源下,包括LDO在内的总功耗仅为95nW,从而实现了电源块的超低功耗工作。无电阻参考电路没有外部电容的LDO稳定性导致一个非常紧凑的设计,占地仅0.033 mm2。所提出的布局后参考和LDO模块分别仅消耗38nA和41nA,在1.2V电源下调节0.9V输出。
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An ultra low-power capacitor-less LDO with high PSR
A compact high PSR Low Drop-Out (LDO) voltage regulator providing a peak load-current (IL) of 100μA is realized in 0.13μm CMOS 1P6M process. Ultra low-power operation is achieved for the power block by realizing a nano-power bandgap reference circuit whose total power consumption including LDO is only just 95nW for 1.2Vsupply. The resistor-less reference circuit with no external capacitor for LDO stability results in a very compact design occupying just 0.033 mm2. The proposed post-layout reference and LDO block consumes only 38nA and 41nA respectively, regulating output at 0.9V with a 1.2V supply.
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