FPGA implementation of hamming code for increasing the frame rate of CAN communication

Controller Area Network (CAN) protocol utilizes Cyclic Redundancy Check (CRC) code as a self-correcting method to detect and correct errors. The main objective of this algorithm is to use an alternative error correction scheme which is called as the Hamming code, replacing the conventional CRC code. Moreover, to possibly increase the CAN's frame rate of the system. The bit's positions of the redundant bits ‘r’ and the bit streams of the frames from the start-of-frame (SOF) to the control bit frames are determine. These bits will be fed into the redundant bit controller to compute for the necessary r. The redundant bit's positions are in power of 2, and will be calculated using modulo-2 operation. This proposed method is synthesized using Xilinx Virtex-5 FPGA. The simulation results shows a significant increase of CAN's frame rate and, it minimizes the bits stuffing payload and can be a better option for detecting and correcting error in CAN System.