Dark-Silicon Inspired Energy Efficient Hierarchical TDM NoC

In this paper, we propose a dark-silicon inspired hierarchical Time-Division-Multiplexing (TDM) network-on-chip (NoC) with online distributed setup-scheme for slots allocation. In addition to the normal mesh routers, we propose hierarchical routers, making use of the dim silicon parts of the chip, to hierarchically connect quad-routers units. Normal routers operate at full-chip-frequency at supply of 1. 2V, while hierarchical routers operate at half-chip-frequency and supply of 0.8V with double datawidth and half slot-size. Routers follow a proposed architecture that distinguishes between data-path and control-setup sub-routers. This allows separate clocking and operating supplies between data and control and to keep the control as a single-slot-cycle design independent of the data slot size. The proposed NoC architecture as well as a base NoC architecture from state-of-the-art are evaluated under uniform random traffic using Synopsys VCS and synthesized using Synopsys Design Compiler for SAED90nm technology. With the same power budget of the base NoC, the proposed architecture provides up to 74% improved setup latency, 32% increased NoC saturation load, and 21% higher success rates. The proposed hierarchical quad is based on leveraging the dim silicon parts of the chip for an energy efficient design. Though it consumes 1.78 times the area of the base quad, however with 56% under-clocked area operating at half the maximum chip frequency; thus reducing the power density to 52% of the base NoC.