{"title":"12b105msample /s, 850mw模数转换器","authors":"C. Michalski","doi":"10.1109/VLSIC.2000.852892","DOIUrl":null,"url":null,"abstract":"This analog-to-digital converter achieves a minimum sampling rate of 105 Msample/S at a total power dissipation of 850 mW while achieving 11.0 effective number of bits (SNR=68 dB) and an SFDR of >80 dB for sampling analog input frequencies up to 70 MHz. The converter uses a switched capacitor multi-bit per stage architecture and incorporates an on-chip differential input buffer, a dedicated track/hold amplifier and an internally compensated wideband differential reference amplifier. The converter is fabricated on a 0.6 /spl mu/m BiCMOS process.","PeriodicalId":6361,"journal":{"name":"2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103)","volume":"19 1","pages":"208-211"},"PeriodicalIF":0.0000,"publicationDate":"2000-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"A 12 b 105 Msample/s, 850 mW analog to digital converter\",\"authors\":\"C. Michalski\",\"doi\":\"10.1109/VLSIC.2000.852892\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This analog-to-digital converter achieves a minimum sampling rate of 105 Msample/S at a total power dissipation of 850 mW while achieving 11.0 effective number of bits (SNR=68 dB) and an SFDR of >80 dB for sampling analog input frequencies up to 70 MHz. The converter uses a switched capacitor multi-bit per stage architecture and incorporates an on-chip differential input buffer, a dedicated track/hold amplifier and an internally compensated wideband differential reference amplifier. The converter is fabricated on a 0.6 /spl mu/m BiCMOS process.\",\"PeriodicalId\":6361,\"journal\":{\"name\":\"2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103)\",\"volume\":\"19 1\",\"pages\":\"208-211\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2000-06-15\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIC.2000.852892\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.2000.852892","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 12 b 105 Msample/s, 850 mW analog to digital converter
This analog-to-digital converter achieves a minimum sampling rate of 105 Msample/S at a total power dissipation of 850 mW while achieving 11.0 effective number of bits (SNR=68 dB) and an SFDR of >80 dB for sampling analog input frequencies up to 70 MHz. The converter uses a switched capacitor multi-bit per stage architecture and incorporates an on-chip differential input buffer, a dedicated track/hold amplifier and an internally compensated wideband differential reference amplifier. The converter is fabricated on a 0.6 /spl mu/m BiCMOS process.
京公网安备 11010802042870号
京ICP备2023020795号-1
分享
求助内容：
应助结果提醒方式：
扫码关注我们
