{"title":"多核功能缓存模拟器","authors":"P. Ratanaworabhan","doi":"10.1109/ECTICON.2012.6254278","DOIUrl":null,"url":null,"abstract":"This paper presents the design and construction of a light-weight execution-driven cache simulator for multicore CPU. We implement the simulator as a Pin tool, running on top of Pin, a dynamic instrumentation tool developed by Intel. We then use it to study the cache behavior of 13 multithreaded programs selected from the two well-recognized benchmark suites, SPLASH2 and PARSEC. We plan to release the tool as open-source software and hope that the computer architecture research community would benefit from it.","PeriodicalId":6319,"journal":{"name":"2012 9th International Conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology","volume":"62 1","pages":"1-4"},"PeriodicalIF":0.0000,"publicationDate":"2012-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Functional cache simulator for multicore\",\"authors\":\"P. Ratanaworabhan\",\"doi\":\"10.1109/ECTICON.2012.6254278\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents the design and construction of a light-weight execution-driven cache simulator for multicore CPU. We implement the simulator as a Pin tool, running on top of Pin, a dynamic instrumentation tool developed by Intel. We then use it to study the cache behavior of 13 multithreaded programs selected from the two well-recognized benchmark suites, SPLASH2 and PARSEC. We plan to release the tool as open-source software and hope that the computer architecture research community would benefit from it.\",\"PeriodicalId\":6319,\"journal\":{\"name\":\"2012 9th International Conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology\",\"volume\":\"62 1\",\"pages\":\"1-4\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2012-05-16\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2012 9th International Conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ECTICON.2012.6254278\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 9th International Conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ECTICON.2012.6254278","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
This paper presents the design and construction of a light-weight execution-driven cache simulator for multicore CPU. We implement the simulator as a Pin tool, running on top of Pin, a dynamic instrumentation tool developed by Intel. We then use it to study the cache behavior of 13 multithreaded programs selected from the two well-recognized benchmark suites, SPLASH2 and PARSEC. We plan to release the tool as open-source software and hope that the computer architecture research community would benefit from it.
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