一个61.5dB SNDR的流水线ADC，使用简单的高可扩展环形放大器

2012 Symposium on VLSI Circuits (VLSIC) Pub Date : 2012-06-13 DOI:10.1109/VLSIC.2012.6243775

B. Hershberg, S. Weaver, Kazuki Sobue, S. Takeuchi, K. Hamashita, U. Moon

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引用次数: 25

摘要

提出了一种基于环形放大器的流水线ADC，它使用由小型逆变器和电容器组成的简单单元来进行放大。基本环形放大器结构的特点是高度可扩展，功率效率高，抗压缩(固有轨对轨输出摆动)。该原型10.5位ADC采用0.18μm CMOS技术，在30MHz采样率下实现61.5dB SNDR，功耗为2.6mW, FoM为90fJ/转换步长。

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A 61.5dB SNDR pipelined ADC using simple highly-scalable ring amplifiers

A ring amplifier based pipelined ADC is presented that uses simple cells constructed from small inverters and capacitors to perform amplification. The basic ring amplifier structure is characterized and demonstrated to be highly scalable, power efficient, and compression-immune (inherent rail-to-rail output swing). The prototype 10.5-bit ADC, fabricated in 0.18μm CMOS technology, achieves 61.5dB SNDR at a 30MHz sampling rate and consumes 2.6mW, resulting in a FoM of 90fJ/conversion-step.

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2012 Symposium on VLSI Circuits (VLSIC)

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