{"title":"利用非线性电荷阱突触器件的自举和预强调充电的高线性向量矩阵乘法器","authors":"Se-Won Yun, Young-Taek Ryu, K. Kwon","doi":"10.1109/MWSCAS47672.2021.9531895","DOIUrl":null,"url":null,"abstract":"In this paper, we propose a neuromorphic Vector Matrix Multiplier (VMM) with high linearity based on charge-trap (CT) synaptic device. From the analysis on the non-linearity of drain current in CT-based VMM cell with respect to drain voltage and the amount of charges stored in the floating gate (FG), a coupling capacitor, Cgdx, is added between the gate and drain nodes to mitigate the non-linearity induced by drain voltage. The WL and DL drivers are kept floating during the read operation for effective coupling. As a result, the linear drain voltage range has been extended from 0.2V to 0.9V when evaluated with signal-to-noise ratio (SNR) or effective number of bits (ENOB). Pre-emphasis amount of charges is injected to FG to compensate non-linearity of drain current dependence of threshold voltage. The linearity on a 128x128 VMM array has improved by above 3.56 ENOB in average over 0.9V swing of drain voltage and 2.0V swing of threshold voltage.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"112 1","pages":"441-444"},"PeriodicalIF":0.0000,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"High Linearity Vector Matrix Multiplier using Bootstrapping and Pre-Emphasis Charging of Non-linear Charge-Trap Synaptic Devices\",\"authors\":\"Se-Won Yun, Young-Taek Ryu, K. Kwon\",\"doi\":\"10.1109/MWSCAS47672.2021.9531895\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, we propose a neuromorphic Vector Matrix Multiplier (VMM) with high linearity based on charge-trap (CT) synaptic device. From the analysis on the non-linearity of drain current in CT-based VMM cell with respect to drain voltage and the amount of charges stored in the floating gate (FG), a coupling capacitor, Cgdx, is added between the gate and drain nodes to mitigate the non-linearity induced by drain voltage. The WL and DL drivers are kept floating during the read operation for effective coupling. As a result, the linear drain voltage range has been extended from 0.2V to 0.9V when evaluated with signal-to-noise ratio (SNR) or effective number of bits (ENOB). Pre-emphasis amount of charges is injected to FG to compensate non-linearity of drain current dependence of threshold voltage. The linearity on a 128x128 VMM array has improved by above 3.56 ENOB in average over 0.9V swing of drain voltage and 2.0V swing of threshold voltage.\",\"PeriodicalId\":6792,\"journal\":{\"name\":\"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)\",\"volume\":\"112 1\",\"pages\":\"441-444\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2021-08-09\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/MWSCAS47672.2021.9531895\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MWSCAS47672.2021.9531895","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
High Linearity Vector Matrix Multiplier using Bootstrapping and Pre-Emphasis Charging of Non-linear Charge-Trap Synaptic Devices
In this paper, we propose a neuromorphic Vector Matrix Multiplier (VMM) with high linearity based on charge-trap (CT) synaptic device. From the analysis on the non-linearity of drain current in CT-based VMM cell with respect to drain voltage and the amount of charges stored in the floating gate (FG), a coupling capacitor, Cgdx, is added between the gate and drain nodes to mitigate the non-linearity induced by drain voltage. The WL and DL drivers are kept floating during the read operation for effective coupling. As a result, the linear drain voltage range has been extended from 0.2V to 0.9V when evaluated with signal-to-noise ratio (SNR) or effective number of bits (ENOB). Pre-emphasis amount of charges is injected to FG to compensate non-linearity of drain current dependence of threshold voltage. The linearity on a 128x128 VMM array has improved by above 3.56 ENOB in average over 0.9V swing of drain voltage and 2.0V swing of threshold voltage.