用于环形振荡器I/Q接收机相位噪声消除的数字锁相环

2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits) Pub Date : 2016-06-15 DOI:10.1109/VLSIC.2016.7573500

Zuow-Zun Chen, Yilei Li, Yen-Cheng Kuan, B. Hu, C. Wong, Mau-Chung Frank Chang

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引用次数: 8

摘要

提出了一种用于环形振荡器I/Q接收机的数字相位噪声消除技术。从数字锁相环(DPLL)中提取环形振荡器相位噪声，包括电源诱发的相位噪声，用于在数字域恢复随机旋转的基带信号。采用65nm CMOS技术制作的接收器原型在1MHz偏置时实现了相位噪声从-88到-109dBc/Hz的降低，在2.4GHz工作时实现了集成相位噪声(IPN)从-16.8到-34.6dBc的降低。

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Digital PLL for phase noise cancellation in ring oscillator-based I/Q receivers

A digital phase noise cancellation technique for ring oscillator-based I/Q receivers is presented. Ring oscillator phase noise, including supply-induced phase noise, is extracted from digital phase-locked loop (DPLL) and used to restore the randomly rotated baseband signal in digital domain. The receiver prototype fabricated in 65nm CMOS technology achieves phase noise reduction from -88 to -109dBc/Hz at 1MHz offset, and an integrated phase noise (IPN) reduction from -16.8 to -34.6dBc, when operating at 2.4GHz.

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2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)

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