Cascadable thyristor optoelectronic switch operating at 50 Mbit/sec with 7.2 femtoJoule external optical input energy

Abstract

Most optoelectronic switches are characterized by a trade-off between the optical input sensitivity, the operation frequency and the area on chip. Fast operation usually occurs at the expense of sensitivity, or else requires considerable chip area for fast amplification in several stages of the input signal. It has recently been shown that specially designed optical thyristors, called depleted thyristors, are not subject to this trade-off [1], The thyristor layer structure must be conceived such that the device can be depleted of carriers by a negative anode-to-cathode voltage pulse. Such structure has intrinsically high speed capabilities, which can be combined with extreme optical input sensitivity by using differential pairs of thyristors instead of single thyristors [2]. The differential pair (Fig. 1) consists of two thyristors A and B connected in parallel, which have a common series resistance Rc [3]. When thyristor A is on and thyristor B is off, the differential switch is in the "1" state; with A off and B on the switch is in the "0" state. The thyristor in the on-state emits light. This allows cascaded operation using the same type of optical thyristor pair both for the emitting and the receiving side of optical interconnects, or for optical computing.