{"title":"A High Throughput/Gate AES Hardware Architecture by Compressing Encryption and Decryption Datapaths - Toward Efficient CBC-Mode Implementation","authors":"Rei Ueno, S. Morioka, N. Homma, T. Aoki","doi":"10.1007/978-3-662-53140-2_26","DOIUrl":null,"url":null,"abstract":"","PeriodicalId":394286,"journal":{"name":"Workshop on Cryptographic Hardware and Embedded Systems","volume":"12 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-08-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"32","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Workshop on Cryptographic Hardware and Embedded Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1007/978-3-662-53140-2_26","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
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