A. Yúfera, A. Rueda, J. Huertas, L. París, T. Osés
{"title":"ALSAC, an automatic layout system for successive approximation converters","authors":"A. Yúfera, A. Rueda, J. Huertas, L. París, T. Osés","doi":"10.1109/CICCAS.1991.184374","DOIUrl":null,"url":null,"abstract":"A new system for the automatic layout of Successive Approximation Charge Redistribution Converters is presented. This system, ALSAC, is able to handle several converter architectures, thus providing designers with a wide flexibility. For all these architectures, ALSAC generates compact layouts preserving matching and symmetry properties, and improving both the area efficiency and performance in comparison with previously reported systems. ALSAC uses a new floorplanning strategy and two module generators. The floorplanning algorithm makes use of slicing structures while considering constraints imposed by the coexistence of analog and digital circuitry in the same IC. The module generators provide the system with very compact realizations of Binary Weighted Capacitor (BWC) and Scaled Switch (SS) Arrays for different specifications and design rules from different foundries.<<ETX>>","PeriodicalId":119051,"journal":{"name":"China., 1991 International Conference on Circuits and Systems","volume":"14 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1991-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"China., 1991 International Conference on Circuits and Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICCAS.1991.184374","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
A new system for the automatic layout of Successive Approximation Charge Redistribution Converters is presented. This system, ALSAC, is able to handle several converter architectures, thus providing designers with a wide flexibility. For all these architectures, ALSAC generates compact layouts preserving matching and symmetry properties, and improving both the area efficiency and performance in comparison with previously reported systems. ALSAC uses a new floorplanning strategy and two module generators. The floorplanning algorithm makes use of slicing structures while considering constraints imposed by the coexistence of analog and digital circuitry in the same IC. The module generators provide the system with very compact realizations of Binary Weighted Capacitor (BWC) and Scaled Switch (SS) Arrays for different specifications and design rules from different foundries.<>