Mohd Ziauddin Jahangir, P. Chandra Sekhar, M. Sikander, J. V. Krishna
{"title":"Design and Implementation of FPGA based DDS-ADPLL for Resonant Frequency Tracking in Sensors","authors":"Mohd Ziauddin Jahangir, P. Chandra Sekhar, M. Sikander, J. V. Krishna","doi":"10.1109/CONECCT55679.2022.9865678","DOIUrl":null,"url":null,"abstract":"This work presents the design and FPGA implementation of a Sine-Wave DDS- All-Digital PLLs for resonant sensors application. The sensor consisting of a mechanical structure. The proposed PLL was designed to track changes in the resonant frequency of a mechanical structure under different spatial orientations. The expected resonant frequency of the mechanical structure under test is less than 10 KHz. As most CMOS PLL ICs operate at very high frequencies, it is not suitable to be used in this application. Additionally, a digital implementation of PLL is preferred due it’s high degree of configurability. In this work, the architecture and design of two different sine wave DDS ADPLLs are presented. A Type-1 sine wave DDS ADPLL was realized on FPGA using SPI ADCs & DACs for interfacing. The important design considerations for realizing proposed ADPLL on the hardware are also presented in this work. The realized ADPLL exhibited a perfect locking behavior around 7KHz center frequency.","PeriodicalId":380005,"journal":{"name":"2022 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CONECCT55679.2022.9865678","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
This work presents the design and FPGA implementation of a Sine-Wave DDS- All-Digital PLLs for resonant sensors application. The sensor consisting of a mechanical structure. The proposed PLL was designed to track changes in the resonant frequency of a mechanical structure under different spatial orientations. The expected resonant frequency of the mechanical structure under test is less than 10 KHz. As most CMOS PLL ICs operate at very high frequencies, it is not suitable to be used in this application. Additionally, a digital implementation of PLL is preferred due it’s high degree of configurability. In this work, the architecture and design of two different sine wave DDS ADPLLs are presented. A Type-1 sine wave DDS ADPLL was realized on FPGA using SPI ADCs & DACs for interfacing. The important design considerations for realizing proposed ADPLL on the hardware are also presented in this work. The realized ADPLL exhibited a perfect locking behavior around 7KHz center frequency.