A methodology to evaluate architectures for real-time control

Abstract

An analytical method of evaluating architectures for real-time control is presented. The methodology allows the examination of an architecture's ability to handle parallelism and synchronization within a real-time execution environment. The architectural models developed are a von Neumann machine with a scheduler/supervisor run time, a very-long-instruction-word machine with a static compiler directed run-time environment, and a dataflow machine with a hardware supported run-time environment. It is shown how a system designer can examine a given architecture's ability to handle the target application with respect to parallelism and task synchronization