{"title":"Investigation of Substrate Noise Coupling and Isolation Characteristics for a 0.35UM HV CMOS Technology","authors":"W. Pflanzl, E. Seebacher","doi":"10.1109/MIXDES.2007.4286198","DOIUrl":null,"url":null,"abstract":"This paper presents the characterization of substrate noise coupling and the isolation capability of ohmic substrate contacts in a HV CMOS technology. Layout variations of contact sizes, distances, and several p+ guard structures are subject of this research. Metal shielded DUT fixtures have been developed to improve the reliability and accuracy of the measurements. All test cases are fabricated with a 0.35 mum HV CMOS technology (Vmax <= 120 V). This process features high resistive native substrate (20 Ohm.cm) together with a 0.5 Ohm.cm pwell. The modeling section describes the distributed substrate \"resistor\" and the DUT fixture behavior.","PeriodicalId":310187,"journal":{"name":"2007 14th International Conference on Mixed Design of Integrated Circuits and Systems","volume":"19 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 14th International Conference on Mixed Design of Integrated Circuits and Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MIXDES.2007.4286198","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
This paper presents the characterization of substrate noise coupling and the isolation capability of ohmic substrate contacts in a HV CMOS technology. Layout variations of contact sizes, distances, and several p+ guard structures are subject of this research. Metal shielded DUT fixtures have been developed to improve the reliability and accuracy of the measurements. All test cases are fabricated with a 0.35 mum HV CMOS technology (Vmax <= 120 V). This process features high resistive native substrate (20 Ohm.cm) together with a 0.5 Ohm.cm pwell. The modeling section describes the distributed substrate "resistor" and the DUT fixture behavior.
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