Novel technique for P-hit single-event transient mitigation using enhance dummy transistor

Abstract

As technology down scales, single event transient (SET) is more vulnerable than before in combinational circuits. This paper proposes a novel layout technique to mitigate the SET effect in combinational circuits. Based on 65nm CMOS process, technology computer aided design (TCAD) SET simulations are conducted on conventional layout, source-isolation layout, dummy transistor layout and the proposed layout. Heavy ions with different liner energy transfer (LET) values, inject angles and striking locations are simulated. The results indicate that, the proposed layout have considerable effect on decreasing the SET pulse width than other layouts. Compare with dummy transistor the proposed enhance dummy transistor have no additional area cost.