Modified CSA-CIA for Reducing Propagation Delay

Abstract

An adder is a fundamental component of various Very Large-Scale Integration (VLSI) circuits like Central Processing Unit (CPU), Arithmetic Logic Unit (ALU), Memory Access Unit (MAU) etc. A various number of operations can be achieved by adders such as addition, subtraction, multiplication, division, exponentiation etc. The basic circuit of the adder is designed using logic gates. The demand for high-performance VLSI systems are increasing rapidly for use in small and portable devices. The speed related to operation depends upon the delay of the adder as it happens to be one of the most fundamental components of all the computing units and it is a very important parameter for high performance. There have been so many research works on reducing the delay associated with the adder. In this paper, we have done a comparative study of Carry Save Adder (CSA) and Carry Increment Adder (CIA) and proposed a hybrid adder circuit to decrease the delay associated with the adder to an optimum level. As CIA has favorable performance regarding propagation delay and CSA also happens to have good performance in higher bit operations. A simulation study has been carried out for comparative study, the coding has been done using Verilog hardware description language (HDL) and the simulation has been realized with the help of Xilinx ISE 14.7 environment. The result shows the effectiveness of the hybrid circuit proposed for propagation delay improvement.