Driving Analog Mixed Signal Verification through Verilog-AMS

Abstract

The complexity of today's SoCs and applications are driving the need for faster and more accurate mixed signal verification. Additionally the percentage of analog content in mixed-signal designs is increasing rapidly. This requires a change in mindset: no longer can the analog and digital modules be verified independantly. For these reasons Accellera has been leading the development of the Verilog-AMS standard, to enable accurate mixed signal design verification of systems containing thousands of analog/digital interface connections. The presentation will discuss the recent language enhancements that have been driven by the Verilog-AMS technical committee, to make system level analysis of analog and mixed signal designs much more efficient and accurate.