{"title":"DSP-RAM: A logic-enhanced memory architecture for communication signal processing","authors":"Z. Wang, B. Cockburn, D. Elliott, W. Krzymień","doi":"10.1109/PACRIM.1999.799579","DOIUrl":null,"url":null,"abstract":"In this paper a new parallel computational RAM (C/spl middot/RAM) architecture, called DSP-RAM, is proposed to speed up a class of digital signal processing (DSP) algorithms in telecommunications. The proposed architecture integrates memory and single instruction stream, multiple data stream (SIMD) parallel processing into a single chip. Key elements of the architecture were designed to verify their cost in silicon area. A software simulator was written in C++ to evaluate the performance of DSP-RAM implementations of critical components in the ITU G.728 voice coding standard.","PeriodicalId":176763,"journal":{"name":"1999 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PACRIM 1999). Conference Proceedings (Cat. No.99CH36368)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1999-08-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"1999 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PACRIM 1999). Conference Proceedings (Cat. No.99CH36368)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/PACRIM.1999.799579","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 9
Abstract
In this paper a new parallel computational RAM (C/spl middot/RAM) architecture, called DSP-RAM, is proposed to speed up a class of digital signal processing (DSP) algorithms in telecommunications. The proposed architecture integrates memory and single instruction stream, multiple data stream (SIMD) parallel processing into a single chip. Key elements of the architecture were designed to verify their cost in silicon area. A software simulator was written in C++ to evaluate the performance of DSP-RAM implementations of critical components in the ITU G.728 voice coding standard.
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