Implementation of parallel processors with wafer scale integration

Abstract

The use of a design strategy employing a hierarchy of structures, each with its own fault circumvention strategy can greatly improve the yield of WSI. The paper examines two strategies for use at the macrocell level in implementing parallel processors. The two basic types of pooled macrocell redundancy are: 1 from N, and many from N. The use of either of these two strategies results in a premium being placed on the interconnect, which is often taken for granted. The paper demonstrates that the interconnect is a vital part of any macrocell pooled redundancy scheme.<>