A droop measurement built-in self-test circuit for digital low-dropout regulators

Abstract

Today's highly integrated system-on-chips (SOCs) employ several integrated voltage regulators to achieve higher power efficiency and smaller board area. Testing of voltage regulators is essential to validate the final product. In this work, we present a unique droop measurement built-in self-test (BIST) circuit for digital low-dropout regulators (DLDOs). The proposed BIST system is capable of storing transient droop information with less than 1.05 % error for droop voltages ranging from 45 mV to 520 mV for nominal DLDO output voltage of 1.6 V where supply voltage is 1.8 V. Additionally, a reuse based 10-bit successive-approximation (SAR) analog-to-digital converter (ADC) is incorporated to generate a digital output corresponding to the stored droop information as the BIST measurement result. The on-chip DLDO decoupling capacitor (∼1 nF) is reconfigured as a charge scaling array for ADC operation during testing to increase reusability. The proposed BIST circuit is designed with 0.18 μm CMOS process in Cadence Virtuoso and verified with corner simulations.