Design and implementation of non-volatile memory express

Abstract

Flash-memory-based solid-state disks (SSDs) provide faster random access and data transfer rates than electromechanical drives and today it can often serve as rotating-disk replacements, but the host interface to SSDs remains a performance bottleneck and also I/O subsystem causes unnecessary latencies, translations in the Read/Write commands. In order to completely utilize the performance of SSDs a Non Volatile Memory Subsystem was designed based on the NVM Express Specification. The communication to this I/O subsystem is through PCI Express interface and the command set is based on NVMe 1.0c Specification. The designed sub-system typically consists of PCIe Core, PCIe controller, NVMe controller, NAND Flash Controller and several NAND Chips. The present paper deals with the design and implementation of PCIe controller and the NVMe controller. The PCIe controller was designed as a generic bridge between any PCIe device and the PCIe Core. The NVMe controller was designed as a PCIe device which implements the NVMe Specification.