Linearity characterization of nano-scale underlap SOI MOSFETs

Abstract

This work presents the linearity characterization by varying the process parameters of new underlap Silicon-on-Insulator (SOI) MOSFETs (with high-k stack on spacer) in single gate (SG) and double gate (DG) configurations. Using linearity defined in-terms of third order intercept (IP3), the paper presents guideline for optimum value of spacer “s”, film thickness “T_si”and doping gradient “d” to maximize the linearity of new underlap design. Based on a new Figure-of-Merit (FoM) involving intrinsic gain A_v, IP3, maximum oscillation frequency f_MAX and dc power consumption P_DC, it has been found that FoM in DG configuration is almost three times higher than that of SG design. This is due to a combination of higher value of f_MAX, A_v and IP3 in DG configuration with power consumption of ~ 2.1 mW. The higher value of FoM in DG device has been achieved at similar “on” to “off” current ratio (I_on/I_off) as specified in current International Technology Road map for Semiconductors (ITRS).