D. Xi, Chen Zeng, W. Liu, Xiang Liu, L. Wan, Heejong Kim, Luyao Wang, C. Kao, Q. Xie
{"title":"A PET detector module using FPGA-only MVT digitizers","authors":"D. Xi, Chen Zeng, W. Liu, Xiang Liu, L. Wan, Heejong Kim, Luyao Wang, C. Kao, Q. Xie","doi":"10.1109/NSSMIC.2013.6829063","DOIUrl":null,"url":null,"abstract":"Multi-voltage threshold (MVT) is an amplitude-based sampling method. It takes timing samples when the event pulse crosses the user-defined thresholds. Only a few comparators and TDCs are required when implementing such digitizer. Previously, we have demonstrated an FPGA-only MVT digitizer based on this method. The FPGA-only MVT digitizer employs the differential I/Os in an FPGA as the required comparators and FPGA based TDCs. The implementation of this digitizer is entirely based on the FPGA. We have demonstrated that it is possible to implement a significant number of MVT digitizers by using a single FPGA. It is also flexible, as it allows us to readily modify, or add functions to, the implementation without requiring costly hardware changes. Currently, we are developing a PET detector module using the FPGA-only MVT digitizer. In this paper we describe the design and implementation of the detector module and report its performance properties. The detector module has a total detection sensitive area of 50mm × 50mm, an overall energy resolution of 15.1% FWHM at 511keV, and a module-level coincidence timing resolution of 684ps FWHM. In addition, our preliminary imaging with such detector module successfully resolves 1.6mm-diameter rods separated by 3.2mm.","PeriodicalId":246351,"journal":{"name":"2013 IEEE Nuclear Science Symposium and Medical Imaging Conference (2013 NSS/MIC)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 IEEE Nuclear Science Symposium and Medical Imaging Conference (2013 NSS/MIC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/NSSMIC.2013.6829063","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 10
Abstract
Multi-voltage threshold (MVT) is an amplitude-based sampling method. It takes timing samples when the event pulse crosses the user-defined thresholds. Only a few comparators and TDCs are required when implementing such digitizer. Previously, we have demonstrated an FPGA-only MVT digitizer based on this method. The FPGA-only MVT digitizer employs the differential I/Os in an FPGA as the required comparators and FPGA based TDCs. The implementation of this digitizer is entirely based on the FPGA. We have demonstrated that it is possible to implement a significant number of MVT digitizers by using a single FPGA. It is also flexible, as it allows us to readily modify, or add functions to, the implementation without requiring costly hardware changes. Currently, we are developing a PET detector module using the FPGA-only MVT digitizer. In this paper we describe the design and implementation of the detector module and report its performance properties. The detector module has a total detection sensitive area of 50mm × 50mm, an overall energy resolution of 15.1% FWHM at 511keV, and a module-level coincidence timing resolution of 684ps FWHM. In addition, our preliminary imaging with such detector module successfully resolves 1.6mm-diameter rods separated by 3.2mm.