High Performance Energy Efficient CMOS Voltage Level Shifter Design

Ravi Nandan Ray, M. M. Tripathi, Chaudhary Indra Kumar
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Abstract

This paper presents an energy efficient voltage CMOS voltage level shifter. Voltage level shifter is used for multi-supply design applications. The main purpose of voltage level shifter is to convert the voltage level from one level to another. We verified our voltage level shifter in ASAP7 7nm Fin-Fet technology. The proposed voltage level shifter is based on differential cascade voltage switch logic, which takes an input voltage in the range of 0.25V to 0.6V and provides an output of 0.7V. Our voltage level shifter improves propagation delay and power dissipation with 48% and 43%, respectively, with recently reported Wilson current mirror voltage level shifter with Zero-Vth design. The proposed design technique comes up with significantly lower power consumption and drastically reduced propagation delay over a wide range of temperatures (-25 to 25 degree Celsius), as compared to existing technologies.
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高性能高能效CMOS电压电平转换器设计
本文提出了一种高效节能的CMOS电压电平移位器。电压电平移位器用于多电源设计应用。电压电平转换器的主要用途是将电压电平从一个电平转换到另一个电平。我们在ASAP7 7nm Fin-Fet技术中验证了我们的电压电平移位器。所提出的电压电平移位器基于差分级联电压开关逻辑,其输入电压范围为0.25V至0.6V,输出电压为0.7V。我们的电压电平移位器将传输延迟和功耗分别提高了48%和43%,最近报道了采用Zero-Vth设计的Wilson电流镜像电压电平移位器。与现有技术相比,所提出的设计技术具有显着降低的功耗,并且在广泛的温度范围内(-25至25摄氏度)大大减少了传播延迟。
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