InGaAs Double-gate fin-sidewall MOSFET

Abstract

InGaAs Double-gate MOSFETs with fins as narrow as 12 nm were fabricated using precision dry etching and digital etch. The primary goal is to use the subthreshold characteristics of long-channel devices to characterize the interface of etched InGaAs fin sidewalls. We have investigated the impact of forming gas anneal, high-K oxide and number of digital etch cycles following RIE. Our results indicate a minimum interface state density (D_it) of ~ 3×10¹² cm^-2eV^-1 obtained in fin sidewalls with Al₂O₃ and HfO₂ oxides after 4 cycles of digital etch. This is equivalent to results reported on planar devices and bodes well for future Trigate MOSFETs that will not require a barrier semiconductor covering the sidewalls.