Boundary scan access of built-in self-test for field programmable gate arrays

Abstract

We discuss issues associated with system level access of Built-In Self-Test (BIST) for Field Programmable Gate Arrays (FPGAs) via the Boundary Scan Interface. In addition, we describe the design of an Application Specific Integrated Circuit (ASIC) which serves as an interface between a PC parallel port and the Test Access Port (TAP) of one or more FPGAs to reprogram the FPGA(s) and administer BIST during off-line testing. We also include a brief description of the FPGA BIST architecture and operation.