Some considerations in the circuit design of large-scale e.c.l. arrays

Abstract

The development of uncommitted logic arrays in e.c.l. has led to the consideration of the most suitable type of cell and its organisation. This paper discusses the factors involved in the choice of a suitable circuit configuration for such a cell. Multilevel long tailed pair trees are compared with a single-level circuit. It is shown that the multilevel arrangement has advantages of less power dissipation and a need for only one phase of the input signals. There is frequently also some speed advantage, though this is dependent on the particular circuit adopted, and may be non-existent.