Fast Image Convolution and Pattern Recognition using Vedic Mathematics on Field Programmable Gate Arrays (FPGAs)

Abstract

A major part of image processing involves convolution process. The pattern recognition techniques which are implemented through Convolutional Neural Networks (CNN) also involves two-dimensional (2D) convolution. The 2D convolution process consists of enormous multiplication operation, which need to be implemented in real time. There is a requirement of fast multiplier for the same operation. Vedic multiplier proved to be faster compared to the conventional multiplication operation. A 2D convolution-based pattern recognition system, which makes use of Vedic Multipliers is proposed in this paper. The proposed system is implemented on Field Programmable Gate Arrays (FPGA) with Verilog programming. The results of Vedic multiplier based convolution and pattern recognition are compared with the conventional multiplier such as Booths algorithm multiplier. The parametric comparison is done in terms of Number of Slice LUT's, Number of Slice Registers, speed and frequency of operation. Results show that there is significant improvement in above said parameters for Vedic multiplier-based convolution in pattern recognition system.