Dynamic Bus Voltage Configuration in a Two-Stage Multi-Phase Buck Converter to Mitigate Transients

Arnab Acharya, V. I. Kumar, S. Kapat
{"title":"Dynamic Bus Voltage Configuration in a Two-Stage Multi-Phase Buck Converter to Mitigate Transients","authors":"Arnab Acharya, V. I. Kumar, S. Kapat","doi":"10.1109/APEC.2019.8722175","DOIUrl":null,"url":null,"abstract":"This paper proposes a dynamic bus voltage transition technique in a two-stage multi-phase buck converter for 48 V to point-of-load (PoL) applications. The proposed topology uses a bank of pre-charged switching capacitors at the output of the first-stage buck converter. This configuration helps to achieve an immediate intermediate bus voltage transition while supplying a (second-stage) multi-phase buck converter. This can substantially speed-up a large-signal transient recovery by adjusting the bus voltage to its highest voltage level. Thereafter, near steady-state, the bus voltage is set to its (lower) optimum value for improving the overall efficiency and also for ripple cancellation for the second-stage converter. A higher bus voltage helps in proportionally reducing the output capacitance for the second-stage while retaining the (voltage) undershoot within the desired limit. This helps to reduce recovery time and current overshoot during a step-reference transient. A hardware prototype of the proposed architecture is made, and improved performance is demonstrated using simulation and experimental results.","PeriodicalId":142409,"journal":{"name":"2019 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 IEEE Applied Power Electronics Conference and Exposition (APEC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/APEC.2019.8722175","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3

Abstract

This paper proposes a dynamic bus voltage transition technique in a two-stage multi-phase buck converter for 48 V to point-of-load (PoL) applications. The proposed topology uses a bank of pre-charged switching capacitors at the output of the first-stage buck converter. This configuration helps to achieve an immediate intermediate bus voltage transition while supplying a (second-stage) multi-phase buck converter. This can substantially speed-up a large-signal transient recovery by adjusting the bus voltage to its highest voltage level. Thereafter, near steady-state, the bus voltage is set to its (lower) optimum value for improving the overall efficiency and also for ripple cancellation for the second-stage converter. A higher bus voltage helps in proportionally reducing the output capacitance for the second-stage while retaining the (voltage) undershoot within the desired limit. This helps to reduce recovery time and current overshoot during a step-reference transient. A hardware prototype of the proposed architecture is made, and improved performance is demonstrated using simulation and experimental results.
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
两级多相降压变换器的动态母线电压配置以减轻瞬变
本文提出了一种用于48 V到负载点(PoL)应用的两级多相降压变换器的动态母线电压转换技术。所提出的拓扑结构在第一级降压变换器的输出端使用一组预充电的开关电容器。这种配置有助于在提供(第二级)多相降压转换器的同时实现立即的中间母线电压转换。通过将总线电压调整到其最高电压水平,这可以大大加快大信号瞬态恢复。此后,在接近稳态时,母线电压被设置为其(较低)最优值,以提高整体效率,也用于第二级变换器的纹波消除。较高的母线电压有助于按比例降低第二级的输出电容,同时将(电压)欠冲保持在所需的限制范围内。这有助于减少在阶跃参考瞬态期间的恢复时间和电流超调。给出了该架构的硬件原型,并通过仿真和实验结果验证了其性能的提高。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 去求助
来源期刊
自引率
0.00%
发文量
0
期刊最新文献
An Integrated Regulated Resonant Switched-Capacitor DC-DC Converter For PoL Applications A manifold microchannel heat sink for ultra-high power density liquid-cooled converters Ultra-High Power Density Magnetic-less DC/DC Converter Utilizing GaN Transistors A High-Efficiency Super-Junction MOSFET based Inverter-Leg Configuration using a Dual-Mode Switching Technique A 6-level Flying Capacitor Multi-level Converter for Single Phase Buck-type Power Factor Correction
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1