A High-Speed and SPA-Resistant Implementation of ECC Point Multiplication Over GF(p)

Abstract

In this paper, we propose a novel high-speed and SPA-resistant architecture for elliptic curve cryptography (ECC) point multiplication. A new Karatsuba-Ofman based pipelined multiplier is proposed to lower the latency, and an improved comb point multiplication method is employed to reduce the clock cycles and to resist simple power analysis (SPA). The proposed ECC architecture has been implemented on Altera's Stratix II FPGA platform. Implementation results show that our processor can perform 256-bit ECC point multiplication in 0.16 ms at the cost of 14.2k ALMs. Compared with the previous implementations, our implementation achieves a speed up factor of no less than 4 times without compromising the SPA-resistance.