Design of a novel multi-rate QC-LDPC decoder

Abstract

Based on layered decoding and semi-parallel structure, a novel architecture of multi-rate QC-LDPC decoder is proposed in this paper. It can support any code rates without any changes in hardware to achieve higher hardware utilization. The update of current layer and the comparison of next layer are processed simultaneously to improve the throughput. The check-to-variable messages are stored indirectly to reduce the storage space. Based on the proposed architecture, a QC-LDPC decoder of 2304 bits and 6-encodings style is presented. Then ModelSim SE6.0 simulation results verify that the proposed decoder is correct and effective. Finally, the decoder is synthesized by Synopsys Design Compiler on SMIC 0.18 µm CMOS technology, and the maximum throughput can achieve 318 Mbps at 145 MHz and 15 iterations.