Analysis and Optimization of Thermal Effect on STT-RAM Based 3-D Stacked Cache Design

Abstract

Spin-Transfer Torque Random Access Memory (STT-RAM) has been proved a promising emerging nonvolatile memory technology suitable for many applications such as cache memory of CPU. Simulation results show that the switching time of Magnetic Tunnel Junction (MTJ), which is the core element of the STT-RAM cell, varies when the temperature changes. In this paper, we study the thermal effect on switching time of STT-RAM cell, and it is showed that when temperature changes from 300K to 375K, the required write pulse period to achieve 10-8 bit error rate (BER) increases from 10.02ns to 15.04ns under 45nm technology. When STT-RAM is used as 3-D stacked L3 cache, the required write pulse period ranges from 11.42ns to 14.68ns due to temperature variation caused by the CPU core layer. If the thermal effect is not considered, the BER of the hottest region will significantly increase to 10-4. Based on these observations, an optimization design with Dynamic Temperature Aware Write Access is proposed, to increase the efficiency of accessing a 3-D stacked STT-RAM cache, as well as achieve the target BER. Compared to a conventional design, the proposed scheme can improve the CPU performance by 3.8% and reduce the write energy consumption of the STT-RAM cache by 4.8%.