VHDL description of self-checking logic circuits

Abstract

The mainstream of current digital circuit design strategy is top-down, where the design process is divided into many phases. A designer starts with a high level description of a circuit, e.g. VHDL, and goes through the design phases to reach mask layout level. This paper develops a set of rules that can be applied to any VHDL description of a logic circuit such that the synthesized gate level circuit is self-checking. Therefore, for a given VHDL description of a logic circuit these rules will transform/modify the existing VHDL code into another equivalent code such that the resulting synthesized circuit will be self-checking. Such a VHDL code is called self-checking VHDL.