Solution to an architectural problem in parallel computing

Abstract

The author presents a solution to the previously unsolved problem of how to construct an array processor with N processing elements, N memory modules, and an interconnection network that allows parallel access and alignment of rows, columns, diagonals, contiguous blocks, and distributed blocks of N*N arrays. The solution leads to an array processor that is both simple and efficient in two critical respects: the memory system uses the minimum number of memory modules to achieve conflict-free memory access and is able to compute N addresses with O(log N) logic gates in O(1) time. The interconnection network is multistage with O(N log N) logic gates, and it can align any of these data vectors for store/fetch, as well as for subsequent processing with a single pass through the network.<>