Banshee: A Fast LLVM-Based RISC-V Binary Translator

Samuel Riedel, Fabian Schuiki, Paul Scheffler, Florian Zaruba, L. Benini
{"title":"Banshee: A Fast LLVM-Based RISC-V Binary Translator","authors":"Samuel Riedel, Fabian Schuiki, Paul Scheffler, Florian Zaruba, L. Benini","doi":"10.1109/ICCAD51958.2021.9643546","DOIUrl":null,"url":null,"abstract":"System simulators are essential for the exploration, evaluation, and verification of manycore processors and are vital for writing software and developing programming models in conjunction with architecture design. A promising approach to fast, scalable, and instruction-accurate simulation is binary translation. In this paper, we present Banshee, an instruction-accurate full-system RISC-V multi-core simulator based on LLVM-powered ahead-of-time binary translation that can simulate systems with thousands of cores. Banshee supports the RV32IMAFD instruction set. It also models peripherals, custom ISA extensions, and a multi-level, actively-managed memory hierarchy used in existing multi-cluster systems. Banshee is agnostic to the host architecture, fully open-source, and easily extensible to facilitate the exploration and evaluation of new ISA extensions. As a key novelty with respect to existing binary translation approaches, Banshee supports performance estimation through a lightweight extension, modeling the effect of architectural latencies with an average deviation of only 2 % from their actual impact. We evaluate Banshee by simulating various compute-intensive workloads on two large-scale open-source RISC-V manycore systems, Manticore and MemPool (with 4096 and 256 cores, respectively). We achieve simulation speeds of up to 618 MIPS per core or 72 GIPS for complete systems, exhibiting almost perfect scaling, competitive single-core performance, and leading multi-core performance. We demonstrate Banshee's extensibility by implementing multiple custom RISC-V ISA extensions.","PeriodicalId":370791,"journal":{"name":"2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCAD51958.2021.9643546","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3

Abstract

System simulators are essential for the exploration, evaluation, and verification of manycore processors and are vital for writing software and developing programming models in conjunction with architecture design. A promising approach to fast, scalable, and instruction-accurate simulation is binary translation. In this paper, we present Banshee, an instruction-accurate full-system RISC-V multi-core simulator based on LLVM-powered ahead-of-time binary translation that can simulate systems with thousands of cores. Banshee supports the RV32IMAFD instruction set. It also models peripherals, custom ISA extensions, and a multi-level, actively-managed memory hierarchy used in existing multi-cluster systems. Banshee is agnostic to the host architecture, fully open-source, and easily extensible to facilitate the exploration and evaluation of new ISA extensions. As a key novelty with respect to existing binary translation approaches, Banshee supports performance estimation through a lightweight extension, modeling the effect of architectural latencies with an average deviation of only 2 % from their actual impact. We evaluate Banshee by simulating various compute-intensive workloads on two large-scale open-source RISC-V manycore systems, Manticore and MemPool (with 4096 and 256 cores, respectively). We achieve simulation speeds of up to 618 MIPS per core or 72 GIPS for complete systems, exhibiting almost perfect scaling, competitive single-core performance, and leading multi-core performance. We demonstrate Banshee's extensibility by implementing multiple custom RISC-V ISA extensions.
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Banshee:一个快速的基于llvm的RISC-V二进制转换器
系统模拟器对于探索、评估和验证多核处理器是必不可少的,并且对于编写软件和开发与体系结构设计相结合的编程模型至关重要。二进制翻译是一种快速、可扩展且指令准确的模拟方法。在本文中,我们提出了Banshee,一个指令精确的全系统RISC-V多核模拟器,基于llvm驱动的提前二进制转换,可以模拟具有数千核的系统。女妖支持RV32IMAFD指令集。它还对现有多集群系统中使用的外设、自定义ISA扩展和多层次、主动管理的内存层次结构进行建模。Banshee与主机架构无关,完全开源,易于扩展,便于探索和评估新的ISA扩展。作为现有二进制翻译方法的一个关键创新,Banshee通过轻量级扩展支持性能评估,对架构延迟的影响进行建模,与实际影响的平均偏差仅为2%。我们通过在两个大型开源RISC-V多核系统,Manticore和MemPool(分别具有4096和256核)上模拟各种计算密集型工作负载来评估Banshee。我们实现了高达每核618 MIPS或完整系统72 GIPS的模拟速度,展示了几乎完美的扩展,具有竞争力的单核性能和领先的多核性能。我们通过实现多个自定义RISC-V ISA扩展来演示Banshee的可扩展性。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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