Channel complexity analysis for reconfigurable VLSI/WSI processor arrays

[1990] Proceedings of the International Conference on Application Specific Array Processors Pub Date : 1990-09-05 DOI:10.1109/ASAP.1990.145470

P. Rhee, J. H. Kim

引用次数: 1

Abstract

The authors propose a general method to analyze channel complexity for a 2D array with a given domain constraint. A domain-based reconfiguration scheme can be divided into two phases: assignment and interconnection. In the assignment phase a logical cell is assigned to a fault-free cell under a domain constraint by assignment rules. In the interconnection phase connections between the assigned logical cells are determined. A domain may be decided considering predetermined maximum distance between two logically adjacent cells. Interconnection redundancy, is represented by channel complexity, where channel complexity is measured by the number of tracks and associated switches. The array is partitioned into as small units, called subranges, as possible while preserving the characteristics of array reconfigurability. Channel complexity is analyzed based on subranges.<>

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可重构VLSI/WSI处理器阵列的信道复杂度分析

提出了一种分析给定域约束下二维阵列信道复杂度的通用方法。基于域的重构方案可分为两个阶段:分配阶段和互联阶段。在分配阶段，根据分配规则将逻辑单元在域约束下分配给无故障单元。在互连阶段，确定分配的逻辑单元之间的连接。可以考虑两个逻辑相邻单元之间的预定最大距离来确定域。互连冗余由信道复杂性表示，其中信道复杂性由轨道和相关交换机的数量来衡量。在保持阵列可重构特性的同时，该阵列被尽可能地分割成称为子范围的小单元。基于子范围分析了信道复杂度。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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[1990] Proceedings of the International Conference on Application Specific Array Processors

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