{"title":"TD-SCDMA system frequency synthesizer design","authors":"Wei Lin, Shizhen Huang, G.-Q. Tong, Wei Lin","doi":"10.1109/ICCT.2008.4716235","DOIUrl":null,"url":null,"abstract":"This paper give a design of a TD-SCDMA frequency synthesizer using multi-ring phase-locked loop, its output frequency has the very good precision and stability.The specific circuit is simulation using 0.5 um BICMOS technology and Cadence SpectreRF. The performance of whole frequency synthesizer is: its output frequency range is 2010 MHz - 2025 MHz, the frequency changing of stride is 200 KHz, the frequency locking time is smaller than 20 us, the power voltage is 3.3 V, the power consumption is 63.26 mW.","PeriodicalId":259577,"journal":{"name":"2008 11th IEEE International Conference on Communication Technology","volume":"2 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 11th IEEE International Conference on Communication Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCT.2008.4716235","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
This paper give a design of a TD-SCDMA frequency synthesizer using multi-ring phase-locked loop, its output frequency has the very good precision and stability.The specific circuit is simulation using 0.5 um BICMOS technology and Cadence SpectreRF. The performance of whole frequency synthesizer is: its output frequency range is 2010 MHz - 2025 MHz, the frequency changing of stride is 200 KHz, the frequency locking time is smaller than 20 us, the power voltage is 3.3 V, the power consumption is 63.26 mW.
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