High-speed bus signal integrity compliance using a frequency-domain model

Abstract

A new technique for frequency-domain compliance testing of high-speed differential interfaces is implemented in a signal integrity simulation tool that can accurately predict a channel's bit-error rate (BER) from seven frequency-domain parameters. This greatly increases the speed and efficiency of designing the number of computer systems required for custom configurations in scale-out data centers. The compliance method is tested with three example case studies in channel printed circuit board (PCB) design. These three studies are: finding maximum loss due to routable trace length as a function of wiring depth layer (which affects crosstalk), finding the maximum routable length when introducing reflections and crosstalk due to adding a connector in the channel, and finding what amount of skew introduced by asymmetry in a differential pair for reasons such as the glass weave or different copper lengths under which a channel can still operate. The pass/fail frequency compliance results are discussed and compared with the time-domain simulation results of the channels tested.