Logical design of a redundant binary adder

Abstract

This paper investigates the logical design of a redundant binary adder with two input digits and one output digit, all in the digit set {1, 0, 1}. Redundant binary arithmetic structures in which all digit sets are {1, 0, 1} were first discussed by Avizienis in 1961. Borovec studied the logical design of a class of such binary adders and subtracters in 1968. At that time, a variation of the adder/subtracter was overlooked. This paper studies the logical design of this variation. The sum digit is still a function only of the digits in three adjacent digital positions of the operands. "Coupled don't cares" are encountered, but have not introduced too much difficulty. The nine distinct formats (under permutation and negation) of representing three values with two bits given by Robertson are used. The simplest adder/subtracter designs from this variation are less complex than the simplest designs previously known.