Young Kwon Kim, D. B. Lee, Won Hyeok Choi, Taesik Park, Myoung Jin Lee
{"title":"Experimental Study for Gate Trap and Generation Current using DCIV Method","authors":"Young Kwon Kim, D. B. Lee, Won Hyeok Choi, Taesik Park, Myoung Jin Lee","doi":"10.18770/KEPCO.2016.02.02.223","DOIUrl":null,"url":null,"abstract":"The newly proposed analysis method using a direct-current current-voltage (DCIV) simulation is introduced for investigating leakage current composing MOS transistor. From comparing the density and location of traps using DCIV method and investigating the leakage current of gate channel transistor, we proposed the graphical analysis method to correlate the DCIV current and leakage mechanism by the traps. And, our graphical method intuitively explains that leakage current in MOS transistor is well correlated with the DCIV current of the MOS transistor arrays due to two kinds of traps created by Fowler-Nordheim (F-N) stress and Hot carrier stress, respectively.","PeriodicalId":445819,"journal":{"name":"KEPCO Journal on electric power and energy","volume":"76 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-06-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"KEPCO Journal on electric power and energy","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.18770/KEPCO.2016.02.02.223","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
The newly proposed analysis method using a direct-current current-voltage (DCIV) simulation is introduced for investigating leakage current composing MOS transistor. From comparing the density and location of traps using DCIV method and investigating the leakage current of gate channel transistor, we proposed the graphical analysis method to correlate the DCIV current and leakage mechanism by the traps. And, our graphical method intuitively explains that leakage current in MOS transistor is well correlated with the DCIV current of the MOS transistor arrays due to two kinds of traps created by Fowler-Nordheim (F-N) stress and Hot carrier stress, respectively.